1. Field of the Invention
The present invention relates generally to computer communication protocols, and more specifically to an integrated protocol that supports both shared memory cache coherence and protected shared nothing message passing.
2. Description of Background Art
One class of multi-processor data computer system consists of a plurality of processor nodes communicating over a high-speed interconnection. Each processor node typically includes a processor and local Random Access Memory (RAM). A computational problem may be divided among processor nodes to use the particular resources available at different processor nodes or to reduce the real time needed to produce a result and thereby expedite the computation. Hence, a process running on one processor node may depend on computations being performed at other processor nodes in the computer system. The various processes communicate over the interconnection to exchange information and synchronize the processes.
There are two major multiprocessor programming paradigms that differ by how the processors communicate with one another. The shared memory paradigm allows all processors to access all memory in the entire machine. Processors communicate with each other by one processor writing a value to a given memory location and another processor reading that value from the same memory location. In contrast, in the shared nothing (or message-passing) paradigm, each processor can only access its own memory, and communicates with other processors by explicitly building messages and sending them to the other processor. Both programming paradigms have their relative merits and both are used. An advantage of the shared-memory paradigm is that it offers more efficient communication, whereas an advantage of the shared-nothing paradigm is that it offers greater protection of one process from all other processes.
Prior art systems usually allow only one or the other programming paradigm. If both are allowed, then they are usually supported over two different types of interconnects, usually a high-performance interconnect for shared memory and the associated cache coherence protocol, and a lower-performance interconnect for message-passing.